Article ID: 000084183 Content Type: Troubleshooting Last Reviewed: 11/27/2015

Arria II Pin Connection Guidelines: Known Issues

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

 Issue 137246: Version 1.8

If the JTAG connections are not used, you need to connect the TDI pin to logic high via a 1-k. resistor, connect TMS to logic high via a 1-k. resistor, tie the TRST pin to GND, and leave TDO unconnected.

Issue 48993: Version 1.6

The Connection Guidelines for VCCCB, VCCA_PLL, VCCA, and VCCH_GXB should all specify the maximum ripple tolerance should be /-5%, not /-5mV.

Resolution

Resolved Issues:

Issue 48993: Version 1.5

Note 14 was corrected in version 1.6 to specify a /-5% tolerance instead of the previously incorrect /-5mV tolerance for the power supply ripple.

Issue 10005634, Version 1.2

Note 12 does not provide all of the details for understanding the I/O module limitations when using SSTL and HSTL I/O standards for Arria® II GX devices. 

Clarifications have been updated for note 12 in versions greater than 1.2.

Related Products

This article applies to 2 products

Arria® II GX FPGA
Arria® II GZ FPGA