Article ID: 000084124 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do I have to connect VREF pin of the I/O bank where mem_clk pins are located when implementing ALTMEMPHY based IP in Arria II GX devices?

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  • Quartus® II Subscription Edition
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    Description

    Yes, you have to connect VREF pin of the I/O bank where mem_clk pins are located to either 0.75V/0.9V when implementing ALTMEMPHY based DDR3/DDR2 SDRAM IP in Arria® II GX devices.

    Although the input buffer of the differential SSTL standard in Arria II GX device is true differential and VREF pin is not needed, the mimic input feedback path(mem_clk only) is using single ended buffer. Hence, you need to ensure the VREF pin of the I/O bank where the mem_clk pins are located is powered up to 0.75V/0.9V for DDR3/DDR2 SDRAM interface respectively.

    Related Products

    This article applies to 1 products

    Arria® II GX FPGA

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