Article ID: 000084123 Content Type: Product Information & Documentation Last Reviewed: 06/04/2014

How can I address the known issues for designs targeting Stratix IV devices in the Quartus II software version 9.0?

Environment

  • Quartus® II Subscription Edition
  • DSP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If you are using Stratix® IV devices, download and install the Quartus® II software 9.0 patch 0.21 to address several known software issues. Recompile your design with the patched software and reconfigure your device with the new programming file.

    Patch 0.21 incorporates the fixes in Quartus II 9.0 patches 0.03, 0.08, and 0.13. If you are using any of those patches, you should install and recompile with patch 0.21 to get all the latest software fixes.

    You can view the readme.txt file for patch 0.21. Download the patch from the appropriate link:

    If you have downloaded and installed patch 0.21, and your design uses multiple RAM blocks and the RAM type of at least one of these memories is AUTO, you must also download and install Quartus II software patch 0.33.

    You can view the readme.txt file for patch 0.33. Download the patch from the appropriate link:

    The Quartus II software 9.0 patch 0.21 addresses the following issues:

    • Version 9.0 allows dual-port dual-clock M144K RAMs, which are not supported in Stratix IV GX ES devices. For more details on this issue, refer to the Stratix IV GX Errata (PDF). M144K RAM blocks in dual-port dual-clock modes may fail to operate correctly, affecting applications such as DCFIFO memories, where data is transferred between two separate clock domains. Patch 0.21 disables the use of dual-port dual-clock modes for all M144K RAMs in Stratix IV GX ES devices.

    • With version 9.0, MLAB RAM blocks in Stratix IV GX ES devices may operate incorrectly when the CRC Error Detection feature is enabled. Read and write operations in MLAB RAM blocks are affected with all CRC Error Detection divisor settings. Patch 0.21 restricts the usage of MLAB memory with the CRC error detection feature in Stratix IV GX ES devices. For more information on this issue, refer to the Stratix IV GX Errata (PDF).

    • If your design uses differential inputs with parallel On Chip Termination (OCT) in version 9.0, parallel OCT is not turned on for the n-pin of the differential pairs during compilation. Patch 0.21 corrects this problem.

    • If your design uses DSP blocks with the chainout feature, the Assembler in version 9.0 sets both the chainout and second adder register to use the same clock and clear signals. The design fails on the board if the chainout and second adder register use different clocks in the design. Patch 0.21 corrects this problem.

    • Patch 0.21 removes the restriction and Fitter error in version 9.0 that you cannot use VCCA set to 2.5V when the reference clock is above 637.5 MHz for high speed interfaces. The Quartus II software version 9.0 generates the following error message in this situation:
      Error: CMU element <name> has an illegal VCCA setting of 2.5V, which is not a legal value.

    • For designs targetting Stratix IV GT devices in version 9.0, Clock Data Recovery (CDR) in the transceiver does not lock in auto mode, resulting in the rx_freqlocked signal being stuck at logic 0 level. Patch 0.21 corrects this problem.

    The Quartus II software 9.0 patch 0.33 addresses the following issue:

    • If you have downloaded and intalled patch 0.21 and your design uses more than one dual clock RAMs and the RAM type of at least one is set to AUTO, your compilation may not complete or you may see a internal error during compilation. Quartus II software patch 0.33 corrects this issue.

     

    These problems will also be fixed in a future release version of the Quartus II software.

    Related Products

    This article applies to 1 products

    Stratix® IV GX FPGA

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