Article ID: 000084113 Content Type: Troubleshooting Last Reviewed: 12/10/2012

Why does the Quartus II software not issue a warning message concerning jitter when a PLL is not driven by its dedicated clock input pin for an Arria V device?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug, current versions of the Quartus® II software will not issue a warning message concerning jitter when a PLL is not driven by its dedicated clock input pin.

    Resolution

    The warning that you should receive in the Quartus II software is:

    Warning (15055): PLL "<PLL Name>" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

    This issue is scheduled to be fixed in a future release of Quartus II software.

    Related Products

    This article applies to 1 products

    Arria® V GX FPGA

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