Description
If a global clock drives both positive-edge triggered logic and negative-edge triggered logic in a MAX device, it needs both global clock nets because the global clock lines are either inverted or not inverted immediately
upon entering a MAX device. Therefore a global clock line can only feed macrocells with its positive value or its negative (inverted) value, but not both, unless a second global clock net is used.
When a different clock signal is applied to a global net in the same design, the following errors will occur during compilation:
Error: "No fit found." Error: "Device requires too many (3/2) global clock signals."
One work-around is to insert an logic cell before the use of each inverted clock. This results in non-global routing of your clock signals, but will allow the clock to drive the appropriate macrocells with the appropriate edge triggering.
Global clock lines in an APEX™ or FLEX® device are inverted on a logic array block (LAB)-by-LAB basis.