Article ID: 000084106 Content Type: Troubleshooting Last Reviewed: 06/10/2015

CRA Interrupt Ports Visible in Arria 10 Hard IP for PCI Express IP Core When CRA Parameter is Disabled

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • Interrupt
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you configure the Arria 10 Hard IP for PCI Express IP core with Avalon-MM interface or Avalon-MM DMA interface and with the Enable control register access (CRA) Avalon-MM slave port parameter turned off, the CraIrq_o interrupt signal, and in Avalon-MM variations, the RxmIrq_<n> interrupt signals, should not be visible at the top level. However, the signals are available.

    Resolution

    This issue has no workaround. You can ignore these interrupt signals. This issue is fixed in version 15.0 of the Arria 10 Hard IP for PCI Express IP core.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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