When you design with the ALTDQ_DQS2 block in a Stratix® V device, you might experience the following error when you synthesize the design:
Error (129001): Input port DQSDISABLEN on atom "|hierarchy|dqs_delay_chain", which is a stratixv_dqs_delay_chain primitive, is not legally connected and/or configured
There is a known problem that requires the DQSDISABLEN and DQSENABLEN ports to be connected to the same internal signal. Otherwise, you will get the synthesis error.
In the altdq_dqs2_stratixv.sv file, connect dqsdisablen and dqsenablen together to the internal signal dqs_enable_int by changing the two lines as follows:
Change lines 967 and 968:
.dqsenable (dqs_enable_int),
.dqsdisablen (dqs_disable_int),
To
.dqsenable (dqs_enable_int),
.dqsdisablen (dqs_enable_int),
Similarly, change lines 1117 and 1,118:
.dqsenable (dqsn_enable_int),
.dqsdisablen (dqsn_disable_int),
To
.dqsenable (dqsn_enable_int),
.dqsdisablen (dqsn_enable_int),
This problem is fixed starting with the Quartus® II software version 12.0.