Article ID: 000084102 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the output data from my Stratix® II DCFIFO megafunction show Xs in a timing simulation?

Environment

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Description

There is a known problem in the gate-level timing simulation netlist generated by the Quartus® II software version 5.0 for third-party simulation tools. This problem prevents your simulation tool from displaying the correct values for the output of a DCFIFO megafunction.

This problem has been fixed beginning with the Quartus II software version 5.1.

You can also contact Altera Technical Support for patch number 1.29 for the Quartus II software version 5.0 SP1.

Related Products

This article applies to 1 products

Stratix® II FPGAs

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