Article ID: 000084099 Content Type: Error Messages Last Reviewed: 07/13/2023

Warning 12283: Assignment INPUT_TERMINATION on transceiver refclk clk buf/pin pcie_ref_clk is not supported

Environment

  • Quartus® II Subscription Edition
  • PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You get this warning in the Quartus® II software if you implement the assignment specified in the Transceiver Clocking in Stratix® V Devices chapter in volume 2 of the Stratix® V Device Handbook. 

    The incorrect setting is:

    set_instance_assignment -name INPUT_TERMINATION OFF -to <refclk_pin_name>

     

    Resolution

    The new recommendation is:

    set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_EXTERNAL_RESISTOR -to <refclk pin name>

     

    This problem is fixed in the latest  Stratix® V Device Handbook.

     

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    This article applies to 5 products

    Stratix® V FPGAs
    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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