Article ID: 000084098 Content Type: Troubleshooting Last Reviewed: 07/01/2013

LPDDR2 Interfaces on Arria V SoC Devices May Fail Postamble Timing

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

This problem affects LPDDR2 products.

Due to preliminary timing models, LPDDR2 interfaces on Arria V SoC devices may fail Postamble Timing in Report DDR.

Resolution

The workaround for this issue is to ignore the postamble timing failures.

This issue will be fixed in a future version.

Related Products

This article applies to 1 products

Arria® V FPGAs and SoC FPGAs

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