Description
You may get set-up time violations when simulating a design that contains a
DCFIFO or LPM_FIFO_DC function due to the inherent design of the function. The circuitry in the design that translates the clock domain is flagged with set-up violations that you can safely ignore.The way to tell if the set-up violations reported are from the DCFIFO or LPM_FIFO_DC function is by the hierarchy path flagged with the error. You can safely ignore errors where the source and destination have separate clocks (the read clock and the write clock for the FIFO). Typically these paths point to the hierarchy path *dcfifo*dffpipe* (where the asterisks are variables). However, you should investigate set-up violations for other hierarchy paths.