Article ID: 000084071 Content Type: Troubleshooting Last Reviewed: 08/09/2023

Why does the Altera Serial RapidIO IP insert more than 31 /A/ characters during IDLE1 sequence?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

An issue has been identified where the Altera® Serial RapidIO® IP can insert mode than the specified maximum of 31 /A/ characters during an IDLE1 sequence.  Whilst no interoperability of physical problems has been identified as a result of this behavior, this issue is technically not in line with the specification.

Resolution

This issue shall be resolved in a future release of the Altera Serial RapidIO IP.

Related Products

This article applies to 29 products

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Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
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Cyclone® II FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® V GT FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
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