Article ID: 000084027 Content Type: Error Messages Last Reviewed: 08/06/2018

Warning (10240): Verilog HDL Always Construct warning at altpciexpav_stif_txresp_cntrl.v

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Quartus® II Subscription Edition
  • Intel® Quartus® Prime Standard Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Arria® 10 Hard IP for PCI Express*, you will see the following warnings during analysis and elaboration when using the Intel® Quartus® II or Intel® Quartus® Prime Standard software.

    Warning (10240): Verilog HDL Always Construct warning at altpciexpav128_txresp_cntrl.v(344): inferring latch(es) for variable "payload_limit_cntr", which holds its previous value in one or more paths through the always construct
    Info (10041): Inferred latch for "payload_limit_cntr[0]" at altpciexpav128_txresp_cntrl.v(344)
    Info (10041): Inferred latch for "payload_limit_cntr[1]" at altpciexpav128_txresp_cntrl.v(344)
    Info (10041): Inferred latch for "payload_limit_cntr[2]" at altpciexpav128_txresp_cntrl.v(344)
    Info (10041): Inferred latch for "payload_limit_cntr[3]" at altpciexpav128_txresp_cntrl.v(344)

    Resolution

    These warning can be safely ignored, and have been fixed in Intel® Quartus® Prime Pro software starting in version 16.1.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.