Article ID: 000084024 Content Type: Troubleshooting Last Reviewed: 02/06/2015

What is the Frequency of the HPS Clocks connected to the FPGA during FPGA Boot before the preloader has run?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

On Cyclone® V and Arria® V SOC devices, if BSEL is set to FPGA boot, or if CSEL= 00 the PLLs are in bypass mode.  The HPS user clocks exported to the FPGA fabric will run at OSC1 Frequency until the PLLs are configured (normally by the Preloader).

 

Resolution This information is scheduled to be included in a future version of the Cyclone V and Arria V Device Handbooks.

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA

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