Article ID: 000084022 Content Type: Troubleshooting Last Reviewed: 07/27/2018

Why do MLAB memory WRITE failures occur in my hardware for my design compiled with the Quartus II software 9.1 and earlier?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

 

You may see this behavior with the Quartus® II software versions 9.1 and earlier when an MLAB is configured without a clock enable, and the LUTRAM does not share the same clock routing as its Datain registers. This condition triggers an Assembler problem that grounds the clock enable of LUTRAM and causes the MLAB to be always disabled for write operations. This error may impact designs targeting Stratix® III, Stratix IV, and Arria® II GX device families.

If your design was compiled with Quartus II software versions 9.1 or earlier, and has run successfully in hardware, it should indicate that the Assembler bug is not triggered and the MLAB failure will not be seen.

 

A patch is available to fix this problem for the Quartus II software version 9.1.  Download and install Patch 0.59 from the appropriate link below and recompile your design.

 

This problem is scheduled to be fixed in a future version of the Quartus II software.

 

Related Products

This article applies to 3 products

Arria® II GX FPGA
Stratix® IV FPGAs
Stratix® III FPGAs

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