Error: device_inst_slave_0_bfm.s0: Slave with readdatavalid signal must support at least 1 pending read

During generation of a Qsys project, a user may get errors when generating Bus Functional Models (BFMs) for standard Avalon interfaces when exporting one or more Avalon® MM master ports from their Qsys project.

The reason behind this error is that the Qsys tool sets incorrect parameters for the BFMs in the testbench project.

To work around this issue, perform the following steps:

1. Within Qsys, for the "Create testbench Qsys system" option, select "Standard, BFMs for standard Avalon interfaces". For the "Create testbench simulation model" option, select "None"
2. Click on the Generate button to generate the testbench project. This will generate a testbench Qsys system.
3. Close the current Qsys project, and open the testbench .qsys project from the testbench/ directory of your project.
4. Modify the parameters for each of the BFM slave instances that have errors to correctly configure the maximum number of pending transactions.
5. In the generation settings of this project for the "Create Simulation Model" select "Verilog". All other settings can be unchecked or set to "None".
6. Click Generate. The simulation files will be placed in the Simulation output directory.

This issue shall be fixed in a later version of the Quartus® II software.