Article ID: 000083954 Content Type: Troubleshooting Last Reviewed: 07/21/2015

Why do I experience intermittent link up problems when using the Stratix V or Arria V GZ Hard IP for PCI Express Gen 2 core?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There is an issue when using the Stratix® V or Arria V GZ Hard IP for PCI Express® IP core, where the link does not consistently come up.  This issue is seen when the core is configured as a native Gen 2 core.  This problem is associated with  the PCIe® Hard Reset Controller (HRC).

    Asserting PERST or Local Reset does not help bring the link up.  Reprogramming the FPGA may allow the link to be brought up, but this is also inconsistent.

    Resolution

    To workaround this issue in Quartus II software version 12.1 SP1, use the following procedure to change to the Soft Reset Controller (SRC):

    For the MegaWizard™ flow:
    1) Edit the <project_dir>/>variant>/synthesis/<variant>.v file
    2) Search for the string, "hip_hard_reset_hwtcl"
    3) Set parameter hip_hard_reset_hwtcl = 0
    4) Save the variant.v
    5) Go to step 7

    For the Qsys flow:
    1) Using a text editor, edit the .qsys file
    2) Search for the string "force_src"
    3) Ensure the following parameters are set as shown below:
      <parameter name="force_hrc" value="0" />
      <parameter name="force_src" value="1" />
    4) Save the changes to the .qsys file
    5) Regenerate the Qsys system to apply the changes made to the underlying design files
    6) Go to Step 7

    Common steps:
    7) Open <project_dir>/<variant>/submodules/sv_xcvr_pipe_native.sv file
    8) Search for "cal_offset_mode"
    9) If the following lines match those in your sv_xcvr_pipe_native.sv file, make the changes as shown in Step 10, otherwise continue to Step 11

       .cal_offset_mode      ((protocol_version == "Gen 2") ? "MODE_ACCUMULATION_MIDSWEEP" : "MODE_INDEPENDENT"),
       .cal_oneshot((protocol_version == "Gen 2") ? "ONESHOT_ON" : "ONESHOT_OFF"),
       .rx_dprio_sel((protocol_version == "Gen 2") ? "RX_CALIBRATION_SEL" : "RX_DPRIO_SEL"),

    10)
       .cal_offset_mode ("MODE_INDEPENDENT"),
       .cal_oneshot  ("ONESHOT_OFF"),
       .rx_dprio_sel ("RX_DPRIO_SEL"),

    11) Recompile design
    12) Search the map report file (eg.top.map.rpt) for hip_hard_reset_hwtcl and ensure the value is set to 0

    Note that making changes to the Qsys system or PCIe core and regenerating may undo some or all the changes.

    This problem is has been fixed in v13.1 of the Quartus II software.

    Related Products

    This article applies to 5 products

    Arria® V GZ FPGA
    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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