Article ID: 000083926 Content Type: Troubleshooting Last Reviewed: 09/30/2013

Why do I see the read data of all High when I read the last address from M20K RAM ?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description This is caused by software issue. Impact of this issue is when you use StratixV device M20K with Single Port RAM and dual clock port mode.
Resolution

Install the patch below for the Quartus II software version 13.0

  • Download the version 13.0 patch 0.45 for Windows (.exe)
  • Download the version 13.0 patch 0.45 for Linux (.tar)
  • Download the Readme for the Quartus II software version 13.0 patch 0.45 (.txt)

This is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 1 products

Stratix® V GX FPGA

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