Description
The Serial RapidIO User Guide implies that the signals arxwlevel, atxovf atxwlevel and buf_av0,1,2,3 only exist in Physical Layer only Serial RapidIO implementations, this is not correct.
These signals always exist but the clock domain changes for IP instances that contain just the Physical Layer or also include the Transport Layer.
When just the Physical Layer is implemented the following clock domains are used:
- arxwlevel - arxclk domain
- atxovf - atxclk domain
- atxwlevel - atxclk domain
- buf_av0,1,2,3 - arxclk domain
When the Transport Layer is also enabled, the arxclk and atxclk become sysclk.
This will be clarified in a future release of the Serial RapidIO User Guide.