Article ID: 000083923 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does an 18x18 bit multiplier take up two 18x18 bit elements in implementation?



In Altera® Stratix® III and IV devices, each DSP half block contains four 18x18 bit signed multipliers, but not all of them can be used during implementation. Each DSP half block has 144 input pins and 72 output pins. An independent 18x18 bit multipiler has an output width of 36 bits, so the DSP half block with 72 output pins can only fit two 18x18 bit multipliers. When creating an independent 18x18 bit multiplier, the tool will actually use two 18x18 bit elements.


The DSP half block multipliers can be used in 9x9, 12x12, 18x18, and 36x36 bit modes. To implement a 10x10 bit multiplier, a 12x12 bit multiplier will be used. However, the resource usage report will show two 18x18 bit elements being used. The 12x12 bit multiplier has an output of 24 bits and the 18x18 bit multiplier has an output of 36 bits. The difference in output widths is 36 - 24 = 12 bits, which is too narrow for another multiplier to use these output pins from the DSP half block.


Implementing three 10x10 bit multipliers will use only four 18x18 elements, and implementing three 18x18 bit multipliers will use only six 18x18 bit elements.

Related Products

This article applies to 3 products

Stratix® IV GX FPGA
Stratix® III FPGAs
Stratix® IV E FPGA



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