1. Replace the existing file altpcietb_pipe32_driver.v and altpcietb_pipe32_hip_interface.v under <your project name>\simulation\submodules with the attached files
2. Set the following parameters to enable PIPE simulation
a. Set parameters hip_ctrl_simu_mode_pipe and enable_pipe32_phyip_ser_driver_hwtcl to 1 in top level testbench when instantiating PCIe Hard IP module
b. Set parameter enable_pipe32_sim_hwtcl to 1 in top level wrapper of PCIe Hard IP module when instantiating altpcie_sv_hip_ast_hwtcl module
Note top_tb is used as the testbench instance name in the two attached files as examples when defining the path HIP_256_PIPEN1B and HIP_INTERFACE respectively.
In altpcietb_pipe32_hip_interface.v:
define HIP_INTERFACE top_tb.dut_pcie_tb.g_altpcie_hip_pipe32_sim_probe.altpcietb_pipe32_hip_interface
Ensure that the testbench instance name (top_tb) is changed to match your design hierarchy.