Article ID: 000083915 Content Type: Troubleshooting Last Reviewed: 11/30/2015

Missing Multi-Cycle Path Timing Constraints in RapidIO IP Core SDC File Cause Timing Violations

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When you compile the RapidIO IP core for an Arria II GZ or Stratix IV device, the Synopsys Design Constraints (.sdc) file that is generated with the IP core cause timing violations. This issue affects all RapidIO IP cores in 1x mode operating at 5 Gbaud and targetting an Arria II GZ or Stratix IV device.

    Resolution

    To fix this issue, manually modify the constraints in the SDC file.

    If your IP core is a 1x variation at 5 Gbaud that targets the Arria II GZ or Stratix IV device family:

    • Add the multi-cycle path constraint set_multicycle_path -end -setup -from [get_cells -compatibility_mode *riophy_dcore|riophy1|init_sm|link_drvr_oe] -to [get_cells -compatibility_mode *riophy_xcvr|riophy_gxb*|transmit_pcs0] 2
    • Add the multi-cycle path constraint set_multicycle_path -end -hold -from [get_cells -compatibility_mode *riophy_dcore|riophy1|init_sm|link_drvr_oe] -to [get_cells -compatibility_mode *riophy_xcvr|riophy_gxb*|transmit_pcs0] 1

    These changes are necessary but might not be sufficient to close timing for your RapidIO IP core. You might need to apply additional strategies. For example, you might need to perform seed sweeping, manually promote divide-by-two clocks and their respective sources as global clocks, disable the divide-by-two clocks as global clocks for shorter routing delay, or perform some combination of these strategies.

    This issue is fixed in version 15.1 of the RapidIO IP core.

    Related Products

    This article applies to 2 products

    Arria® II FPGAs
    Stratix® IV FPGAs

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