Article ID: 000083881 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the minimum peak-to-peak differential input voltage for Cyclone IV GX transceiver input reference clock?

Environment

  • Cyclone® IV GX FPGA
  • Cyclone® IV FPGAs
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The peak-to-peak differential input voltage for Cyclone® IV GX transceiver input reference clock is as following:

    1. Min VID = 100mV
    2. Max VID = 1.6V

    This information will be updated into the future release of the Cyclone IV GX datasheet.

    Resolution

     

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