Article ID: 000083861 Content Type: Troubleshooting Last Reviewed: 01/08/2014

Why does my Configuration via Protocol (CvP) design fail link training and not load the core image when I use a SOF from a Quartus II software version 13.0 or lower in CvP Initialization mode?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There is a known issue with the Convert Programming files conversion of the SRAM Object File (.sof) from Quartus® II software version 12.0 through 12.1sp1. The "Disable EPCS ID check" was enabled from version 12.0 through 12.1sp1 which caused the issue with link training and loading of the core image.

    Resolution

    To workaround this issue in Quartus II software version 12.0 through 12.1 sp1, go to the Advanced tab of the the Convert Programming Files window and check the checkbox labeled "Disable EPCS ID check". 

    In Quartus II software version 13.0 and beyond, the "Disable EPCS ID check" is correctly set to disable.

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA

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