Due to a known problem in the Quartus® II software version 14.1, the parameter editor-generated VHDL file for the Soft LVDS RX Intel FPGA IP with Intel® MAX® 10 devices will not be correct. The rx_in port in the VHDL file generated in the project and simulation directories do not match.
The rx_in port for the synthesis file uses type std_logic but in the simulation file it is std_logic_vector(0 downto 0), which causes simulation to produce an error similar to the one below.
Loading work.mylvds_rx(rtl)
# ** Failure: (vsim-3807) Types do not match between component and entity for port "rx_in".
Replace the rx_in port from std_logic to std_logic_vector(0 downto 0) in ./<design_name>/<design_file>.vhd file
This problem is fixed in Quartus II software version 15.0.