Article ID: 000083856 Content Type: Troubleshooting Last Reviewed: 07/10/2015

Why do I get an error when simulating the VHDL file of the Altera Soft LVDS RX IP, using MAX 10 devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a known problem in the Quartus® II software version 14.1, the MegaWizard Plug-In-generated VHDL file for the Altera® Soft LVDS RX IP with MAX® 10 devices will not be correct. The rx_in port in the VHDL file generated in the project and simulation directories do not match.

    The rx_in port for the synthesis file uses type std_logic but in the simulation file it is std_logic_vector(0 downto 0) which causes simulation to produce an error similar to the one below.

    Loading work.mylvds_rx(rtl)
    # ** Failure: (vsim-3807) Types do not match between component and entity for port "rx_in".

    Resolution

    Replace the rx_in port from std_logic to std_logic_vector(0 downto 0) in ./<design_name>/<design_file>.vhd file

    This problem is fixed in Quartus II software version 15.0.

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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