Article ID: 000083851 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why do I see incorrect read data when using a Hard Memory Controller with multiple MPFE ports?

Environment

    Quartus® II Subscription Edition
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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Description

When performing write and read transactions to the hard memory controller (HMC) MPFE ports, you may observe that the read transactions are performed before the write transactions, even when the write priority is higher. As a result, the read data may be incorrect.

For example, if your HMC MPFE ports are set as follows:

Port0 is configured as write-only, priority set to 7, and weight set to 0
Port1 is configured as read-only, priority set to 1, and weight set to 0

If you perform a write request on Port0 to address 'addr0' with data 'data0' and a read request on Port1 to address 'addr0' simultaneously, the data read back should always be 'data0'. There is a problem in the HMC where the read data is not as expected.

 

Resolution

The workaround is to delay performing read requests to an address range until all write requests to the same address range are completed. An alternative approach is to read from a different region of memory than the one that is being written to.

Related Products

This article applies to 11 products

Cyclone® V ST SoC FPGA
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Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
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Cyclone® V E FPGA
Cyclone® V SE SoC FPGA

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