Article ID: 000083798 Content Type: Product Information & Documentation Last Reviewed: 08/17/2012

How do I transmit XAUI compliant data using Altera transceivers?

Environment

  • Stratix® IV GT FPGA
  • Arria® GX FPGA
  • Arria® II GX FPGA
  • Cyclone® IV GX FPGA
  • Stratix® II GX FPGA
  • Stratix® GX FPGA
  • Stratix® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To transmit XAUI compliant data using Altera® transceivers you must format the data on the tx_datain[63..0] port as shown below.

tx_datain[63..0] = A7A3A6A2A5A1A4A0  B7B3B6B2B5B1B4B0  C7C3C6C2C5C1C4C0

This results in the following transmission over the four lanes.

Lane 0 : A0 A4 B0 B4 C0 C4
Lane 1 : A1 A5 B1 B5 C1 C5
Lane 2 : A2 A6 B2 B6 C2 C6
Lane 3 : A3 A7 B3 B7 C3 C7

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