Article ID: 000083760 Content Type: Troubleshooting Last Reviewed: 12/25/2015

Why is the output data clocked on the wrong edge of the clock?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software version 15.0 and earlier, you may see the IO output register is clocked on the incorrect edge.
    This occurs in Stratix® V designs where the IO output register and IO output enable registers are used and both are clocked on the negative edge of the clock. You will see the data being incorrectly clocked on the rising edge.
    Resolution

    To work around this problem, either use core registers for the output register and output enable register or clock the registers on the rising edge of an inverted clock.

    This problem is scheduled to be fixed in a future release of the Quartus Prime software.


    Related Products

    This article applies to 4 products

    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA
    Stratix® V GX FPGA

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