Description
Due to a problem in the Quartus® II software version 15.0 and earlier, you may see the IO output register is clocked on the incorrect edge.
This occurs in Stratix® V designs where the IO output register and IO output enable registers are used and both are clocked on the negative edge of the clock. You will see the data being incorrectly clocked on the rising edge.
This occurs in Stratix® V designs where the IO output register and IO output enable registers are used and both are clocked on the negative edge of the clock. You will see the data being incorrectly clocked on the rising edge.
Resolution
To work around this problem, either use core registers for the output register and output enable register or clock the registers on the rising edge of an inverted clock.
This problem is scheduled to be fixed in a future release of the Quartus Prime software.
