This error will occur in the Quartus® II software version 2.2 when the I/O Standard of the particular bank where the TDO pin is located conflicts with the JTAG I/O standard.
This problem has been fixed beginning with the Quartus II software version 3.0.
The software problem is related to the I/O standard setting on the TDO output pin of the JTAG block. The Quartus II software sets this pin to use the default I/O standard in the project's compilation settings. The default I/O standard is LVTTL within the Quartus II software.
For example, the above error will occur if the bank where TDO resides is assigned to the HSTL class I standard, but the default I/O standard is set to LVTTL.
To get around the problem in the Quartus II software version 2.2, you can explicitly add the I/O standard assignment (HSTL class I in this example) to the TDO pin "altera_reserved_tdo" within the project's CSF file by adding the following lines:
altera_reserved_tdo : IO_STANDARD = "HSTL CLASS I"; altera_reserved_tdo : LOCATION = Pin_F14;
In the device, the JTAG TDO pin is hard-wired to VCCIO, so it can only drive out the VCCIO voltage level. So regardless of the I/O standard setting in the Quartus II software, the TDO pin will drive VCCIO.
This device limitation may be a problem in certain situations, as the ByteBlaster™ can only accept 2.5 and 3.3 Volts. A workaround for these cases is to either use a level buffer to increase voltage, or to use the ByteBlaster™ II, which is able to handle lower voltages like 1.5 Volts.