Article ID: 000083703 Content Type: Troubleshooting Last Reviewed: 09/11/2013

What clock should I use to capture the PIPE interface signals on the test_out bus when using SignalTap II Logic Analyzer?

Environment

    PCI Express
    Clock
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Description

Use pld8gtxclkout to capture the PIPE signals on the test_out interface using the SignalTap™ II Logic Analyzer.  This clock signal is located in the following hierarchy: 

For Arria® V device families: *xcvr_native|inst_av_pcs|inst_av_pcs_ch*
For Stratix® V device families: *xcvr_native|inst_sv_pcs|int_sv_pcs_ch*

Related Products

This article applies to 11 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA

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