During timing analysis in the Quartus® II software, do my phase-locked loop (PLL) clock settings override my project clock settings for Stratix™ designs?

The following occurs during this situation:

• A warning during compilation will report that the project clock settings override the PLL clock settings.
• The project clock setting overrides the PLL clock settings for timing-driven compilation.
• The compiler will check the lock frequency range of the PLL. If the frequency specified in the project clock settings is outside the lock frequency range, the Quartus II software will not override the PLL clock settings.
• Performing a timing analysis without recompiling your design will not change the programming files. You must recompile your design to update the programming files.
• A Default Required f_MAX setting will not override the PLL clock settings. Only individual clock settings will override the PLL clock settings.

These guidelines will save time with Stratix designs that use features such as clock switchover or PLL reconfiguration because the Quartus II software can perform a timing analysis without recompiling the design.

When the Quartus II software performs a timing analysis for APEX^™ II, APEX 20KE, APEX 20KC, or Mercury^™ designs, the PLL clock settings override the project clock settings.

For more information, you can go to Chapter 12. Transitioning APEX Designs to Stratix Devices of the Stratix Design Handbook or the Quartus II software HELP.