Incorrect results or this port name message may occur when you have two Verilog HDL modules that differ only in case (such as "TEST" and "test" or "Test"). The Quartus II Compiler will only read one of the modules during synthesis. When the compiler reads the instantiation of the other module, it may report that the port names do not exist. If the port names are the same, the compiler will use one module for both instantiations, leading to incorrect results.
This problem is now fixed in current versions of the Quartus II software.
In version 2.1, you should avoid using module names which differ only by case. This problem only applies to module names: you can have a wire named my_wire and another named My_Wire and the compiler will distinguish them correctly.