Article ID: 000083664 Content Type: Troubleshooting Last Reviewed: 04/14/2014

VHDL Postfit Simulation Not Supported for Arria V and Cyclone V Designs with Hard Memory Controller

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects DDR2, DDR3, and LPDDR2 products using hard memory controllers.

    VHDL postfit simulation is not supported for Arria V and Cyclone V designs containing hard memory controllers. You will encounter VHDL elaboration errors due to unconnected ports.

    Resolution

    The workaround for this issue is to use Verilog postfit simulation.

    This issue will not be fixed.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs

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