Due to a problem in the Quartus® II software versions 7.0 and earlier, this command works correctly the first time you run quartus_map, but does not produce correct results if you change the value of the Verilog macro between two synthesis iterations.
This problem is fixed beginning with the Quartus II software version 7.1.
You can use the quartus_map --verilog_macro command line argument to pass the value of a Verilog macro during synthesis of your design. For example, you can create a macro called `intf_width in your design without defining the macro within the source file, and pass a valid value to the macro during compilation with the following command:
quartus_map <project name> --verilog_macro="intf_width=8"
To avoid this problem in version 7.0 or earlier, include all the macros used in your design in a Verilog header file, and add this file to the project files list. Whenever you want to change the value of a specific macro, edit this file instead of changing the value using the --verilog_macro option with the quartus_map command.
Alternatively, you can delete the /db directory for your project, which forces a complete recompilation of your design.