Article ID: 000083589 Content Type: Troubleshooting Last Reviewed: 11/16/2011

IP Compiler for PCI Express Might Exceed Maximum ACK Latency When ASPM L0s is Enabled in Stratix IV Devices

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    ACK Latency is the maximum latency from request receipt to acknowledgement transmission. When ASPM L0s is enabled, the ACK latency might exceed the PCI Express specification limit. This violation can occur when acknowledgement data link layer packets compete with TX transaction layer packets for link access during periods of high TX link utilization. If ASPM L0s is enabled and the link partner requires a high FTS count, the ACK latency can be sufficiently high to trigger retransmission of TX transaction layer packets.

    This issue affects IP Compiler for PCI Express implementations with ASPM L0s enabled that target a Stratix IV device.

    Resolution

    To avoid this issue, disable ASPM L0s in your system.

    This issue will not be fixed in a future version of the IP Compiler for PCI Express.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs

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