Article ID: 000083575 Content Type: Troubleshooting Last Reviewed: 08/22/2023

Why are pins reported as stuck at 1 when I perform Boundary Scan Testing on SOC Devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When performing Boundary Scan Testing on Cyclone® V SOC and Arria® V  SOC Hard Processor Systems (HPS), the HPS must be held in reset.

Resolution

This requirement is scheduled to be included starting with the release 15.1 of the Cyclone® V SOC and Arria® V SOC Handbooks.

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA

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