You may see this critical warning when running a full compilation of DDR3 UniPHY-based controller with the Stratix® III device.
Article ID: 000083573 Content Type: Error Messages Last Reviewed: 11/14/2013
Warning (307026): DDR3-SDRAM pin mem_dqs_to_and_from_the_uniphy_ddr3_0 must be fed by an OUTPUT_PHASE_ALIGNMENT WYSIWYG with either a 90, 72, 108, degree phase shift
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Resolution The phase setting for the output phase alignment block is always calibrated dynamically. So, this warning can be safely ignored.