Article ID: 000083568 Content Type: Troubleshooting Last Reviewed: 11/20/2015

SmartVID Controller IP Core Designs Targeting Arria 10 10AX115 Devices Fail Timing

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The SmartVID Controller IP core designs targeting Arria 10 10AX115 devices experience hold time violation for the following path :

    from

    altera_parallel_smartvid_wrapper:i_altera_parallel_smartvid_wrapper|altera_vid_ctl_wrapper:altera_vid_ip|altera_vid_ctl_fuse:fuse_handling|corectl_jtag_reg

    to

    altera_parallel_smartvid_wrapper:i_altera_parallel_smartvid_wrapper|jtag~cs_css/tck_fo_1_core.reg__nff.

    This issue will cause timing failure.

    This issue affects all designs using the SmartVID Controller IP core versions 14.1 and 14.1 Arria 10 Edition.

    Resolution

    Set this path to false path.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs