Article ID: 000083560 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How should I connect OCT calibratoin pins (Rup and Rdn) in Altera DDR/DDR2/DDR3 High Perfomance Memory Controller design?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

OCT calibration for Altera® DDR/DDR2/DDR3 High Perfomance Memory Controllercan occur in either power-up mode or user mode.

If your design is using power-up mode OCT calibration, you should create these two pins (termination_blk0~_rup_pad and termination_blk0~_rdn_pad) in your design pin planner and assign to available Rup and Rdn pin location available on the FPGA.

If your design is using user mode OCT calibration (which allows you to dynamically control OCT calibration after the device is configured), you should include ALTOCT megafunction in your design and connect Rup and Rdn pins accordingly. You could refer to Altera Application Note AN465 for more information.

Please refer to device handbook or device pin out document on Altera website for Rup and Rdn pin locatoin on the device.

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Stratix® III FPGAs

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