Article ID: 000083539 Content Type: Product Information & Documentation Last Reviewed: 07/17/2014

How do I determine the failing calibration stage for a Cyclone V or Arria V HPS SDRAM controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To view the calibration debug information, you must turn on the debug output report by setting the RUNTIME_CAL_REPORT option to value 1 in the sequencer_defines.h file located in the hps_isw_handoff directory.

 

After boot and during calibration, the following statements will be printed in the debug output report if calibration fails:

 

SEQ.C: Calibration Failed

SEQ.C: Error Stage : <Num>

SEQ.C: Error Substage: <Num>

SEQ.C: Error Group : <Num

 

To determine the stage and sub-stage, open the sequencer.h file in the hps_isw_handoff directory and look for the calibration defines:

 

/* calibration stages */

#define CAL_STAGE_NIL 0

#define CAL_STAGE_VFIFO 1

#define CAL_STAGE_WLEVEL 2

#define CAL_STAGE_LFIFO 3

#define CAL_STAGE_WRITES 4

#define CAL_STAGE_FULLTEST 5

#define CAL_STAGE_REFRESH 6

#define CAL_STAGE_CAL_SKIPPED 7

#define CAL_STAGE_CAL_ABORTED 8

#define CAL_STAGE_VFIFO_AFTER_WRITES 9

/* calibration substages */

#define CAL_SUBSTAGE_NIL 0

#define CAL_SUBSTAGE_GUARANTEED_READ 1

#define CAL_SUBSTAGE_DQS_EN_PHASE 2

#define CAL_SUBSTAGE_VFIFO_CENTER 3

#define CAL_SUBSTAGE_WORKING_DELAY 1

#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2

#define CAL_SUBSTAGE_WLEVEL_COPY 3

#define CAL_SUBSTAGE_WRITES_CENTER 1

#define CAL_SUBSTAGE_READ_LATENCY 1

#define CAL_SUBSTAGE_REFRESH 1

 

Refer to the UniPHY Calibration Stages section of the Functional Description – UniPHY (.PDF) chapter of the External Memory Interface Handbook for details on the calibration stages.

Related Products

This article applies to 5 products

Cyclone® V SX SoC FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA

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