Article ID: 000083465 Content Type: Troubleshooting Last Reviewed: 08/17/2012

When using Active Parallel (AP) configuration mode can the DCLK frequency be set to a fixed frequency or can I use an external clock?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, the AP configuration mode uses the 40MHz internal oscillator for configuration and this cannot be changed nor can an external clock be used.

When using the AP configuration mode the maximum DCLK frequency will be 40MHz. The typical DCLK frequency will be 33MHz with a minimum of 20MHz.

Related Products

This article applies to 2 products

Cyclone® IV E FPGA
Cyclone® III FPGAs

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