Article ID: 000083449 Content Type: Troubleshooting Last Reviewed: 08/29/2014

Can a Global Clock (GCLK) be used as the input clock source for a non-DPA ALTLVDS_RX interface, in Stratix V, Arria V or Cyclone V devices?

Environment

    Quartus® II Subscription Edition
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Description

No, a Global Clock (GCLK) cannot be used as the input clock source for a non-DPA ALTLVDS_RX interface in Stratix® V, Arria® V or Cyclone® V devices. However, due to a known issue in the Quartus® II software version 13.0, no error or warning message is generated if this is implemented.

 

 

Resolution This issue is fixed in Quartus II software version 13.0 SP1. A valid error message will be generated if a Global Clock (GCLK) is used as the input clock source for a non-DPA ALTLVDS_RX interface.

Related Products

This article applies to 16 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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