10001846, Chapter 3 "Specifications", Table 3-2, Version 4.1.
phy_clk_1x phase shift specification has been updated. Stratix® III PLL outputs table incorrectly states that the phase shift of phy_clk_1x out of the PLL counter C0 has a phase shift of 0 Degrees. The correct phase shift for phy_clk_1x implemented by the IP Toolbench is 30 Degrees.
The next revision of the user guide will include this updated specification.