Article ID: 000083445 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Is there a known issue with the Triple Speed Ethernet (TSE) LVDS Receive (Rx) and Transmit (Tx) general purpose PLLs merging in Quartus II software version 10.1?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, the Triple Speed Ethernet IP has enhanced the LVDS Rx PLL reset sequence in Quartus® II software version 10.1. The LVDS Rx PLL now has pll_areset controlled via the tse_lvds_reset_sequencer, whilst the Tx PLL has its pll_areset tied inactive.

    As the input sources to the two PLLs are now different, Quartus II is no longer able to merge the two PLLs.

    This issue will be address in a future version of the IP.

    Related Products

    This article applies to 7 products

    Cyclone® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® IV E FPGA
    Stratix® III FPGAs
    Arria® II GZ FPGA
    Arria® II GX FPGA

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