Article ID: 000083427 Content Type: Troubleshooting Last Reviewed: 09/03/2013

Why does phasedone always appear high after asserting phasestep?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Depending on the voltage-controlled oscillator (VCO) and scanclk frequencies, the phasedone low time may be greater than or less than one scanclk cycle. If you sample the phasedone signal with scanclk, you may miss the low pulse of phasedone.

    Resolution

     

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices