Error-[MPD] Module previously declared

You may see this error in Synopsys VCS or VCS MX when simulating if your design contains two or more IP variations created by the MegaWizard™ Plug-In Manager in the Quartus® II software. This error may occur when your design has multiple variations of the same IP core, or has different IP cores, but the cores have duplicate simulation files. For each IP core, a complete simulation file set is added to the <variation>_sim directory, including some files that may be shared with other IP cores. For example, some SystemVerilog packages may be common to mulitple IP cores.

The error occurs when the concatenated list of all simulation file names for all IP variations (including the duplicate filenames) is added to the VCS command line. The file set does not include copies of the simulation library files that are installed in the <Quartus II installation directory>/eda/sim_lib directory structure.

To work around this issue, perform one of the following steps:

• You can manually eliminate the duplicate file names form the VCS command line by specifying only one file from every set of duplicate files. You can identify the duplicate files by looking for files that have the same name but reside in different directories (for example <variation 1>_sim/foo.sv and <variation 2>_sim/foo.sv). You should also compare the contents of the duplicate filenames to ensure the files are duplicates.

• Alternatively, individually compile each IP simulation file set into its own library by using the vlogan command as documented in the VCS MX User Guide which is included in a VCS MX installation, but not in a VCS (VCSi) installation. You can also obtain the VCS MX User Guide from the Synopsys website. To compile the libraries individually, follow these steps:
  1. Identify all the IP variations and create a directory for each of them. Each directory holds the intermediate VCS library files for its IP variation. For example, if you have two IP variations ip_var1 and ip_var2, create two directories: ./ip_var1_lib and ./ip_var2_lib.
  2. If it does not already exist, create a file called synopsys_sim.setup. This file contains the mapping from logical library names to their physical directory locations. Add the mapping from logical library names to physical directory names for each of the IP variations. For example, for the two IP variations ip_var1 and ip_var2, add the following two lines to the synopsys_sim.setup file:

     ip_var1: ./ip_var1_lib
ip_var2: ./ip_var2_lib

  3. If, in step 2, you add libraries from the Quartus II simulation library directory (<Quartus II installation directory>/eda/sim_lib), create library subdirectories for Altera simulation model libraries and add their mappings to the logical library names in the synopsys_sim.setup file. These libraries are described in the Simulation section in volume 3 of the Quartus II Handbook.
  4. Create a work library by creating a ./work directory and map it to the logical work library and adding the following line to the synopsys_sim.setup file:

     work: ./work

  5. Create a shell script containing the following commands:
     1. For each IP variation, compile all SystemVerilog files by adding the following command:

        vlogan -sverilog -work ip_var1 <any -v, -y, options> <all SystemVerilog source files in the appropriate order>

     2. For each IP variation, compile all standard Verilog HDL files by adding the following command:

        vlogan v2k -work ip_var1 <any -v, -y, define options> <all standard Verilog HDL source files>

     3. Compile Quartus II simulation libraries into separate libraries by either compiling them manually with vlogan commands (similar to compiling the simulation files for each IP variation). Alternatively, compile the Quartus II simulation libraries, using the EDA Simulation Library Compiler by executing the following command:

        quartus_sh --simlib_comp -tool vcsmx -language verilog -family <family>

        For more information about compiling simulation libraries with the EDA Simulation Library Compiler, refer to Compiling Simulation Libraries in the Quartus II Software in Quartus II Help and Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.
  6. Compile your testbench files and any other files into the work library with vlogan commands. For example,

     vlogan -work work <testbench files>

  7. Elaborate the top-level module and the generate simulator executable with the following VCS command:

     vcs <options that do not specify source files> <top module name>

     VCS automatically searches all the libraries specified in the synopsys_sim.setup file for unresolved modules. If you would like more control over the library search order, specify the libraries with the -lib option documented in the VCS MX User Guide.