Article ID: 000083384 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the rx_byteorderalignstatus output port not get asserted on the first occurrence of the byte ordering pattern in Basic double-width configuration in Stratix IV GX device?

Environment

  • Stratix® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Solution

 

For Stratix® IV GX devices, the ALTGX MegaWizard® Plug-in Manager provides an option to select rx_syncstatus output signal based byte ordering. This option is available in the Rate Matcher/Byte Order screen. If this option is selected, the byte ordering block is triggered when rx_syncstatus gets asserted.

 

Altera has identified that during functional simulation in Quartus® II software version 8.0,  the  rx_byteorderalignstatus port does not get asserted on the first occurrence of the byte ordering pattern for the following basic double width mode configuration.

  • FPGA Fabric-Transceiver interface width: 32-bits
  • 8b10b encoder/decoder disabled
  • Word aligner pattern width: 32-bits (ex: 1A2B3C4D)
  • Byte ordering pattern width: 16-bits
  • Byte ordering pattern: 2 LSBytes of the word aligner pattern (ex: 3C4D)

For the above configuration, the byte ordering block receives rx_syncstatus one clock cycle after receiving the word aligned data that contains the byte ordering pattern. Therefore the rx_byteorderalignstatus port does not get asserted on the first occurrence of the byte ordering pattern.

 

Workaround : This issue will be fixed in Quartus® II software version 8.1

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