RapidIO IP Core Variations With an Avalon-MM Slave Module Fail in VHDL Qsys Systems

If you generate a RapidIO IP core instance in Qsys, and specify output language VHDL, your RapidIO IP core cannot connect correctly in the Qsys system.

The reason is the declarations of the word or double-word addresses drbell_s_address, mnt_s_address, sys_mnt_s_address, io_s_rd_address, and io_s_wr_address. In VHDL, these ports are defined to have a bit range whose least significant bit is 2 or 3 rather than 0. Qsys cannot connect these ports correctly.

All RapidIO IP core variations have a system maintenance interface with a sys_mnt_s_address signal. The other signals are available depending on the modules your IP core includes.

This issue has no workaround. You must avoid generating a RapidIO system with output language VHDL in Qsys.

This issue is fixed in version 14.1 of the RapidIO IP core.