Article ID: 000083369 Content Type: Troubleshooting Last Reviewed: 02/15/2013

Incorrect Reset Sequence for Serial Digital Interface

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Long locking time in serial digital interface (SDI) I when receiving high definition (HD) in Arria V and Stratix V devices.

    This issue affects the Triple-Rate video standard in 12.0.

    Resolution

    There is no workaround for this issue.

    This issue is fixed in ACDS patches for 12.0 and 12.1.

    Related Products

    This article applies to 2 products

    Stratix® V FPGAs
    Arria® V FPGAs and SoC FPGAs

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