Due to a change in the behavior of the Quartus® II software, designs that could successfully merge ALTLVDS PLLs in versions 9.1 SP2 and earlier may no longer be able to merge ALTLVDS PLLs in versions 10.0 and later. The change depends on how rx_inclock on the ALTLVDS receiver and tx_inclock on the ALTLVDS transmitter are connected.
If rx_inclock and tx_inclock are driven by the same clock resource in your design, the ALTLVDS PLLs can be successfully merged provided you have satisfied all other requirements for PLL merging (see below).
In the Quartus II software versions 9.1 SP2 and earlier, ALTLVDS PLLs can also be merged if the rx_outclock on the receiver is connected to the tx_inclock on the transmitter and uses the same frequency as rx_inclock on the receiver. Altera no longer considers this configuration to be a valid condition for merging ALTLVDS PLLs beginning with the Quartus II software version 10.0. To allow the ALTLVDS PLLs to be merged, change your design so that the rx_inclock and the tx_inclock are driven by the same clock resource.
If you have an existing design which was compiled in the Quartus II software version 9.1 SP2 or earlier, there is no need to recompile to satisfy the new ALTLVDS PLL merging rules.
ALTLVDS PLL merging requirments:
- Identical clock sources
- Identical pll_areset sources
- If one ALTLVDS instance uses pll_areset, then all instances must use the same pll_areset
- Identical deserialization/serialization factors